ENGR 160 -- Digital Circuits

Instructor:
Esteban Rodriguez-Marek
erodriguezma@ewu.edu
Phone: (509) 359-7004
CEB 332

Announcements:

Power point presentation due in my email inbox Wednesday, March 11, 2009 at 5pm. If you do not get confirmation, call me, or email me again, as you will not be allowed to present (and lose 30%) unless you turn in your presentation on time. Just in case my email gets full (it happens), you may use the following address: erodrigu@gmail.com
Final project and peer reports are due either in my email inbox (same rules as above) or a hard copy in my office by Thursday, March 12, 2009, at 5pm. If I don’t get them by then, you will lose the 70% of the grade for the reports. Please do not forget to turn in a peer/self evaluation report, as described in the handout.

Day-to-Day:

Lecture #	Topics	Reading	HW Assigned	HW Due
Lecture 1	Introduction, number systems, conversions between different number systems	Chapter 1	HW #1
Lecture 2	Binary, Octal and Hexadecimal arithmetic. Radix and diminished radix complements, signed numbers. Twos’ Complement arithmetic.
Lecture 3	Two’s complement arithmetic. Basic logic gates. Huntington postulates.	Chapter 2	HW #2	HW#1 (solutions)
Lecture 4	Theorems of Boolean algebra, DeMorgan’s law, operator precedence, Boolean functions, function complements.	Chapter 3
Lecture 5	Function simplification through Boolean minimization, minterms, maxterms, sum of minterms, product of maxterms (.e. canonical form).	Chapter 4
Lecture 6	Sum of products, product of sums, i.e. standard forms. Non-standard forms. NAND, NOR, XOR, XNOR gates.		HW #3	HW#2 (solutions)
Lecture 7	K-maps	Chapter 5		HW#3 (solutions)
Lecture 8	TEST #1		HW #4
Lecture 9	4 and 5 variable k-maps. POS simplification using K-maps	Chapter 6
Lecture 10	Review of Test #1. NAND gate function implementation.	Section 3.2	HW #5	HW #4 (solutions)
Lecture 11	NOR gate function implementation. XOR gate. Intro to combinational devices.Adders (Half and Full), Subtractors (Half and Full), n-bit Binary Adders/Subtractor
Lecture 12	Code conversion, decoders, function implementation with decoders.	Chapter 9	Hw #6	HW #5 (solutions)
Lecture 13	Encoders. Multiplexers.
Lecture 14	TEST #2
Lecture 15	Introduction to sequential logic, state diagram.		Final Project	HW #6 (solutions)
Lecture 16	SR and D Latches.	Chapter 11
Lecture 17	D flip flop. Design of sequential circuits. JK Flip flops.		Problems with solutions and some sample problems
Tentative Remaining schedule
Lecture 18	State minimization
Lecture 19	Review and questions.
Lecture 20	Project Presentations			Project Report

Dec 10	FINAL EXAM (12:00pm – 2:00pm)

Whack your professor:
Here is a good place to do it!

Lecture Notes: (PDF and MS Word formats)
    View Chapter 1 or download it in MS Word format
    View Chapter 2 or download it in MS Word format
    View Chapter 3 or download it in MS Word format
    View Chapter 4 or download it in MS Word format
    View Chapter 5 or download it in MS Word format

Handouts:

Table of Common Exponents and Bases (you may bring this handout to the test).
Notes on Signed Numbers (pdf) or dowload it in MS Word format.
Extra Problems on Boolean Algebra. Note that not all of this problems may apply to what we have already done, but they will give some more practice exercises in simplification. Note also that an overbar is used for a complement, instead of the usual apostrophe.

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